diff --git a/cpu/arm1176/cpu.c b/cpu/arm1176/cpu.c
index c59a77b..d1a3327 100644
--- a/cpu/arm1176/cpu.c
+++ b/cpu/arm1176/cpu.c
@@ -58,22 +58,6 @@
 	return 0;
 }
 
-
-/* * reset the cpu by setting up the watchdog timer and let him time out */
-void reset_cpu (ulong ignored)
-{
-	printf("reset... \n\n\n");
-	SW_RST_REG = 0x6400;
-	/* loop forever and wait for reset to happen */
-	while (1) {
-		if (serial_tstc()) {
-			serial_getc();
-			break;
-		}
-	}
-	/*NOTREACHED*/
-}
-
 /* flush I/D-cache */
 static void cache_flush (void)
 {
diff --git a/cpu/arm1176/s3c64xx/Makefile b/cpu/arm1176/s3c64xx/Makefile
index 4656d9a..b527939 100644
--- a/cpu/arm1176/s3c64xx/Makefile
+++ b/cpu/arm1176/s3c64xx/Makefile
@@ -28,6 +28,8 @@
 
 LIB	= $(obj)lib$(SOC).a
 
+SOBJS	= reset.o
+
 COBJS-$(CONFIG_S3C6400)	+= cpu_init.o speed.o
 COBJS-y	+= timer.o
 
diff --git a/cpu/arm1176/s3c64xx/reset.S b/cpu/arm1176/s3c64xx/reset.S
new file mode 100644
index 0000000..315b13f
--- /dev/null
+++ b/cpu/arm1176/s3c64xx/reset.S
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2009 Samsung Electronics.
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <s3c6400.h>
+
+.globl reset_cpu
+reset_cpu:
+	ldr	r1, =ELFIN_CLOCK_POWER_BASE
+	ldr	r2, [r1, #SYS_ID_OFFSET]
+	ldr	r3, =0xffff
+	and	r2, r3, r2, lsr #12
+	str	r2, [r1, #SW_RST_OFFSET]
+_loop_forever:
+	b	_loop_forever